1. Field of the Invention
The present invention relates to a serial-parallel type analog-to-digital converter and a serial-parallel type analog-to-digital converting method.
2. Description of Related Art
An analog-to-digital converter for converting an analog signal into a digital signal has been widely used owing to the popularization of digital apparatuses. Also, an enhancement of a processing speed and reduction in power consumption are required for the analog-to-digital converter along with the miniaturization and promotion of inexpensiveness of the recent digital apparatuses. A serial-parallel type analog-to-digital converter for converting and separately dividing an analog signal into a higher bit side and a lower bit side of a digital signal attracts attention as an analog-to-digital converter which is capable of realizing the enhancement of the processing speed and the reduction in power consumption.
Here, FIG. 8 shows an example of the serial-parallel type analog-to-digital converter in the related art. As shown in FIG. 8, the serial-parallel type analog-to-digital converter 101 is composed of a reference voltage generator 102, a higher bit comparing portion 103, a lower bit comparing portion 104, a higher bit side encoder 105, a lower bit side encoder 106, a timing generator 107, and the like. In this case, the reference voltage generator 102 generates a plurality of different reference voltages for comparison, and the higher bit comparing portion 103 compares a voltage of an analog signal with each of corresponding ones, for a higher bit, of the reference voltages (hereinafter referred to as “higher bit reference voltages” when applicable). In addition, the lower bit comparing portion 104 compares the voltage of the analog signal with each of corresponding ones, for a lower bit, of the reference voltages (hereinafter referred to as “lower bit reference voltages” when applicable), and the higher-bit side encoder 105 logically processes output signals from the higher bit comparing portion 103 to output a digital signal on the higher bit side corresponding to the analog signal. In addition, the lower bit side encoder 106 logically processes output signals from the lower bit comparing portion 104 to output a digital signal on a lower bit side corresponding to the analog signal. Also, the timing generator 107 generates control signals in accordance with which the higher bit comparing portion 103 and the lower bit comparing portion 104, the higher bit side encoder 105 and the lower bit side encoder 106, and the like are controlled, respectively.
Here, the reference voltage generator 102 is configured so as to generate the higher bit reference voltages used in the higher bit comparing portion 103, and the lower bit reference voltages used in the lower bit comparing portion 104.
Also, the serial-parallel type analog-to-digital converter 101 is provided with a multiplexer (MUX) 108. In this case, the multiplexer 108 selects the lower bit reference voltages which are used in the lower bit comparing portion 104 in accordance with the result of comparing the voltage of the analog signal with each of the higher bit reference voltages in the higher bit comparing portion 103. Also, the multiplexer 108 is connected in an output portion thereof to the lower bit comparing portion 104.
The lower bit comparing portion 104 is composed of a comparison stage 110, an amplification stage 111, and a comparison/hold section 112. In this case, the comparison stage 110 outputs a difference voltage between the voltage of the analog signal, and the corresponding one of the lower bit reference voltages. The amplification stage 111 amplifies an output signal from the comparison stage 110. Also, the comparison/hold section 112 compares an output signal from the amplification stage 111 with a predetermined threshold, and holds therein the comparison result in the form of data of “0” or “1”. It is noted that the comparison stage 110, the amplification stage 111, and the comparison/hold section 112 are provided by a number corresponding to the number of lower bits to be converted (for example, by 7 when the number of lower bits is 3 bits, and by 15 when the number of lower bits is 4 bits).
As shown in FIGS. 9A and 9B, the comparison stage 110 of the lower bit comparing portion 104 includes a switch SW100, a switch SW102, and a capacitor C100. The corresponding one of the lower bit reference voltages which are each outputted from the multiplexer 108 to a reference voltage input terminal 120 is inputted to one terminal of the capacitor C100. Also, the analog signal is inputted to the other terminal (input portion) of the switch SW100.
Also, when each of the switches SW100 and SW102 is held ion an ON state, and no lower bit reference voltage is inputted from the multiplexer 108 to the one terminal of the capacitor C100, the comparison stage 110 is held in a mode of inputting (applying) the analog signal to the one terminal of the capacitor C100 to sample the analog signal (hereinafter referred to as “a reset mode” when applicable) (refer to FIG. 9A). On the other hand, when each of the switches SW100 and SW102 is held ion an OFF state, and the corresponding one of the lower bit reference voltages is each inputted from the multiplexer 108 to the one terminal of the capacitor C100, the comparison stage 110 is held in a mode of outputting the difference voltage between the voltage of the analog signal and the corresponding one of the lower bit reference voltages from the capacitor C100 to the amplification stage 111 the subsequent stage (hereinafter referred to as “a comparison mode” when applicable) (refer to FIG. 9B).
However, short-circuit is caused between the output portion of the switch SW100 in the comparison stage 110, and the output portion of the multiplexer 108. Thus, there is provided a state in which a parasitic capacitance due to the switch of the multiplexer 108, and a parasitic capacitance parasitic in a wiring extending from the multiplexer 108 to the comparison stage 110 are equivalently connected to the output portion of the switch SW100. As a result, when the comparison stage 110 is held in the reset mode, a load applied to the analog signal (in other words, a load applied to a circuit for outputting the analog signal to the comparison stage 110) increases by these parasitic capacitances (they are each designated with reference symbol Cp of FIGS. 9A and 9B). Along with this increase in load, the processing speed when the analog signal is converted into the digital signal on the lower bit side is reduced.
As described above, in the serial-parallel type analog-to-digital converter 101 in the related art, the short circuit is caused between the output portion of the switch SW100, and the output portion of the multiplexer 108. As a result, the load applied to the analog signal increases, and thus it is difficult to further speed up the operation of the serial-parallel type analog-to-digital converter.
In order to cope with this situation, the applicant of this patent application proposed a serial-parallel type analog-to-digital converter as shown in FIG. 10. That is to say, the serial-parallel type analog-to-digital converter includes a switch SW103 provided between an output portion of a switch SW100 and an output portion of a multiplexer 108, a switch SW104, and an amplifier AMP101. In this case, the switch SW103 is an opening/closing section for performing open/close between the output portion of the switch SW100, and the output portion of the multiplexer 108. The switch SW104 is an input section for inputting therethrough a voltage of an analog signal to the output portion of the multiplexer 108 in a phase of the open state caused between the output portion of the switch SW100, and the output portion of the multiplexer 108 by the switch SW103. Also, the amplifier AMP101 is an amplification section for amplifying the analog signal. This serial-parallel type analog-to-digital converter, for example, is described in Japanese Patent Laid-Open No. 2004-64475.
In this serial-parallel type analog-to-digital converter, the open state can be caused between the output portion of the switch SW100 in the comparison stage 110, and the output portion of the multiplexer 108 by the switch SW103 in the phase of the reset mode in the comparison stage 110. Moreover, it is possible to previously precharge the parasitic capacitances Cp equivalently connected to the output portion of the multiplexer 108 by the switch SW104 and the amplifier AMP101. As a result, the load applied to the analog signal can be lightened by the parasitic capacitance Cp parasitic in the output portion of the switch SW100 in the phase of the reset mode in the comparison stage 110. Moreover, the load applied to the reference voltages in the phase of the comparison mode (in other words, the load applied to the multiplexer 8) can be lightened. As a result, it is possible to speed up the operation of the serial-parallel type analog-to-digital converter.
Now, the comparison stage 110 of the lower bit comparison portion 104 must hold therein the sampled voltage for a time period from a time point when the voltage of the analog signal is sampled in the capacitor C100 to a time point when the higher bit comparing portion 103 outputs a signal based on the comparison result.
Now, a serial-parallel type analog-to-digital converter is known in which in order to effectively utilize such a waiting time period, a plurality of comparison stages are prepared for the lower bit comparing portion 104, and an interleave operation for alternately operating the plurality of comparison stages is performed, thereby enhancing the conversion efficiency.
In the case as well of the serial-parallel type analog-to-digital converter performing such an interleave operation, the provision of the opening/closing section, input section and amplification section described above makes it possible to lighten the load applied to the analog signal or the reference voltages, thereby speeding up the operation of the serial-parallel type analog-to-digital converter.